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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:50:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:50:20 -0700 |
| commit | 295c18bd6b8d3fa503041904f7f7df392a4b5167 (patch) | |
| tree | 9a20c23d61a5c714ca8408c40d2e71345deff088 /techlibs/ecp5/cells_bb.v | |
| parent | 4cc74346f11e96b9a2bce1c984c674a22771a00a (diff) | |
| parent | 6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (diff) | |
| download | yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.tar.gz yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.tar.bz2 yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'techlibs/ecp5/cells_bb.v')
| -rw-r--r-- | techlibs/ecp5/cells_bb.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 223e19b9e..8557053b6 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -664,3 +664,23 @@ module PCSCLKDIV ( ); parameter GSR = "DISABLED"; endmodule + +// Note: this module is not marked keep as we want it swept away in synth (sim use only) +(* blackbox *) +module PUR ( + input PUR +); + parameter RST_PULSE = 1; +endmodule + +(* blackbox, keep *) +module GSR ( + input GSR +); +endmodule + +(* blackbox, keep *) +module SGSR ( + input GSR, CLK +); +endmodule
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