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author | David Shah <dave@ds0.me> | 2018-10-10 16:35:19 +0100 |
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committer | David Shah <dave@ds0.me> | 2018-10-10 16:35:19 +0100 |
commit | 983fb7ff88ab5f398073e2aa1d5e44eb03d01ee3 (patch) | |
tree | 6d1f78a56ae2e3e850b277a4cbc247cbc60ac641 /techlibs/ecp5/brams_map.v | |
parent | 2ef1af8b58c845f4ca070a0469fe42212bcb5eee (diff) | |
download | yosys-983fb7ff88ab5f398073e2aa1d5e44eb03d01ee3.tar.gz yosys-983fb7ff88ab5f398073e2aa1d5e44eb03d01ee3.tar.bz2 yosys-983fb7ff88ab5f398073e2aa1d5e44eb03d01ee3.zip |
ecp5: First BRAM type maps successfully
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/ecp5/brams_map.v')
-rw-r--r-- | techlibs/ecp5/brams_map.v | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v new file mode 100644 index 000000000..894f5c46f --- /dev/null +++ b/techlibs/ecp5/brams_map.v @@ -0,0 +1,47 @@ +module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CFG_ABITS = 10; + parameter CFG_DBITS = 18; + parameter CFG_ENABLE_A = 2; + + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [18431:0] INIT = 18432'bx; + parameter TRANSP2 = 0; + + input CLK2; + input CLK3; + + input [CFG_ABITS-1:0] A1ADDR; + input [CFG_DBITS-1:0] A1DATA; + input [CFG_ENABLE_A-1:0] A1EN; + + input [CFG_ABITS-1:0] B1ADDR; + output [CFG_DBITS-1:0] B1DATA; + input B1EN; + + localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV"; + localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV"; + + localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "NORMAL"; + + + generate if (CFG_DBITS == 1) begin + DP16KD #( + `include "bram_init_1_2_4.vh" + .DATA_WIDTH_A(1), + .DATA_WIDTH_B(1), + .CLKAMUX(CLKAMUX), + .CLKBMUX(CLKBMUX), + .WRITEMODE_A(WRITEMODE_A), + .GSR("DISABLED") + ) _TECHMAP_REPLACE_ ( + `include "bram_conn_1.vh" + .CLKA(CLK2), .CLKB(CLK3), + .WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1), + .WEB(1'b0), .CEB(B1EN), .OCEB(1'b1), + .RSTA(1'b0), .RSTB(1'b0) + ); + end else begin + wire TECHMAP_FAIL = 1'b1; + end endgenerate +endmodule |