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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:52:50 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:52:50 +0200 |
| commit | 0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc (patch) | |
| tree | 24f6a3cd2c4fa19a41d90cd57b0908b668efeb21 /techlibs/ecp5/brams_map.v | |
| parent | 0d60902fd97bba4f231f8f600434b8a69562ffff (diff) | |
| parent | e0a67fce12647b4db7125d33264847c0a3781105 (diff) | |
| download | yosys-0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc.tar.gz yosys-0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc.tar.bz2 yosys-0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc.zip | |
Merge branch 'master' into eddie/pr1352
Diffstat (limited to 'techlibs/ecp5/brams_map.v')
| -rw-r--r-- | techlibs/ecp5/brams_map.v | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v index 0353cbadb..310aedaf2 100644 --- a/techlibs/ecp5/brams_map.v +++ b/techlibs/ecp5/brams_map.v @@ -113,3 +113,45 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); wire TECHMAP_FAIL = 1'b1; end endgenerate endmodule + +module \$__ECP5_PDPW16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CFG_ABITS = 9; + parameter CFG_DBITS = 36; + parameter CFG_ENABLE_A = 4; + + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [18431:0] INIT = 18432'bx; + + input CLK2; + input CLK3; + + input [CFG_ABITS-1:0] A1ADDR; + input [CFG_DBITS-1:0] A1DATA; + input [CFG_ENABLE_A-1:0] A1EN; + + input [CFG_ABITS-1:0] B1ADDR; + output [CFG_DBITS-1:0] B1DATA; + input B1EN; + + localparam CLKWMUX = CLKPOL2 ? "CLKA" : "INV"; + localparam CLKRMUX = CLKPOL3 ? "CLKB" : "INV"; + + localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE"; + + PDPW16KD #( + `include "bram_init_9_18_36.vh" + .DATA_WIDTH_W(36), + .DATA_WIDTH_R(36), + .CLKWMUX(CLKWMUX), + .CLKRMUX(CLKRMUX), + .GSR("AUTO") + ) _TECHMAP_REPLACE_ ( + `include "bram_conn_36.vh" + .CLKW(CLK2), .CLKR(CLK3), + .CEW(1'b1), + .CER(B1EN), .OCER(1'b1), + .RST(1'b0) + ); + +endmodule |