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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:31:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-08 16:31:59 -0700 |
| commit | bca3cf684367ac5cf33ac05506d9e604a325bd3f (patch) | |
| tree | b2b29b441c108984719d0b470ec34b779abec511 /techlibs/ecp5/arith_map.v | |
| parent | f7c7003a193361285ba59d1315c1e7c26c4c52f1 (diff) | |
| parent | e194e65358058f3a039636d2603cc093f7b75e50 (diff) | |
| download | yosys-bca3cf684367ac5cf33ac05506d9e604a325bd3f.tar.gz yosys-bca3cf684367ac5cf33ac05506d9e604a325bd3f.tar.bz2 yosys-bca3cf684367ac5cf33ac05506d9e604a325bd3f.zip | |
Merge branch 'master' into xaig
Diffstat (limited to 'techlibs/ecp5/arith_map.v')
| -rw-r--r-- | techlibs/ecp5/arith_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index 1094c5f8a..eb7947601 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -33,7 +33,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); input CI, BI; output [Y_WIDTH-1:0] CO; - wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); |