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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-10-01 10:57:09 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-01 10:57:09 +0300 |
| commit | d99b1e32618f8aa92c01eb0ac5d08486f411cca0 (patch) | |
| tree | 5671ffa605b5f6b31b86aacb2dbeaacd018302d7 /techlibs/ecp5/abc_model.v | |
| parent | fc56459746fec7751735749e3328378e1089b914 (diff) | |
| parent | d963e8c2c6207ad98d48dc528922ad58c030173f (diff) | |
| download | yosys-d99b1e32618f8aa92c01eb0ac5d08486f411cca0.tar.gz yosys-d99b1e32618f8aa92c01eb0ac5d08486f411cca0.tar.bz2 yosys-d99b1e32618f8aa92c01eb0ac5d08486f411cca0.zip | |
Merge branch 'master' into SergeyDegtyar/anlogic
Diffstat (limited to 'techlibs/ecp5/abc_model.v')
| -rw-r--r-- | techlibs/ecp5/abc_model.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v new file mode 100644 index 000000000..56a733b75 --- /dev/null +++ b/techlibs/ecp5/abc_model.v @@ -0,0 +1,5 @@ +// --------------------------------------- + +(* abc_box_id=2 *) +module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); +endmodule |