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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 10:33:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 10:33:54 -0700 |
| commit | 612083a807f0776f13db132ddbd5cf0bed14eb02 (patch) | |
| tree | 3b9613b57c2e32f90baaee774e9d9231369ac20f /techlibs/ecp5/abc_5g_nowide.lut | |
| parent | 177c26ca359f85d0804c62f73e1df1665ffd1ec5 (diff) | |
| parent | 988e6163abae4ed0a01952c221d17f70bed9c244 (diff) | |
| download | yosys-612083a807f0776f13db132ddbd5cf0bed14eb02.tar.gz yosys-612083a807f0776f13db132ddbd5cf0bed14eb02.tar.bz2 yosys-612083a807f0776f13db132ddbd5cf0bed14eb02.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'techlibs/ecp5/abc_5g_nowide.lut')
| -rw-r--r-- | techlibs/ecp5/abc_5g_nowide.lut | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/ecp5/abc_5g_nowide.lut b/techlibs/ecp5/abc_5g_nowide.lut new file mode 100644 index 000000000..60352d892 --- /dev/null +++ b/techlibs/ecp5/abc_5g_nowide.lut @@ -0,0 +1,12 @@ +# ECP5-5G LUT library for ABC +# Note that ECP5 architecture assigns difference +# in LUT input delay to interconnect, so this is +# considered too + + +# Simple LUTs +# area D C B A +1 1 141 +2 1 141 275 +3 1 141 275 379 +4 1 141 275 379 379 |