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authorEddie Hung <eddie@fpgeh.com>2019-06-14 10:28:30 -0700
committerGitHub <noreply@github.com>2019-06-14 10:28:30 -0700
commit474fe9f47ae9c8a022d726a1b674853ca3236db0 (patch)
tree91907bc7387e194d64d5503dec4bf4c7987593ae /techlibs/ecp5/abc_5g.lut
parentbc22e2e3ee120aeb84323ce52031b895f9f62f54 (diff)
parent95665730540c0fd7c76690f28d0fd6b5f13f2223 (diff)
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Merge pull request #1097 from YosysHQ/dave/xaig_ecp5
Add ECP5 ABC9 support (to xaig branch)
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diff --git a/techlibs/ecp5/abc_5g.lut b/techlibs/ecp5/abc_5g.lut
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+# ECP5-5G LUT library for ABC
+# Note that ECP5 architecture assigns difference
+# in LUT input delay to interconnect, so this is
+# considered too
+
+
+# Simple LUTs
+# area D C B A
+1 1 141
+2 1 141 275
+3 1 141 275 379
+4 1 141 275 379 379
+
+# LUT5 = 2x LUT4 + PFUMX
+# area M0 D C B A
+5 2 151 239 373 477 477
+
+# LUT6 = 2x LUT5 + MUX2
+# area M1 M0 D C B A
+6 4 148 292 380 514 618 618
+
+# LUT7 = 2x LUT6 + MUX2
+# area M2 M1 M0 D C B A
+7 8 148 289 433 521 655 759 759
+