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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-10-01 11:04:32 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-01 11:04:32 +0300 |
| commit | e092c4ae6b60cf67efd16efbfbf739895ad501c0 (patch) | |
| tree | 939a5b94d14a11df511aa95482458b33a1f6139f /techlibs/ecp5/abc_5g.box | |
| parent | 1070f2e90b9ba37856932189ef09a0f2316d9a21 (diff) | |
| parent | d963e8c2c6207ad98d48dc528922ad58c030173f (diff) | |
| download | yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.tar.gz yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.tar.bz2 yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.zip | |
Merge branch 'master' into SergeyDegtyar/efinix
Diffstat (limited to 'techlibs/ecp5/abc_5g.box')
| -rw-r--r-- | techlibs/ecp5/abc_5g.box | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box index c757d137d..a336b4a85 100644 --- a/techlibs/ecp5/abc_5g.box +++ b/techlibs/ecp5/abc_5g.box @@ -15,16 +15,16 @@ CCU2C 1 1 9 3 630 379 630 379 526 275 392 141 273 516 516 516 516 412 412 278 278 43 -# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram) +# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) # Outputs: DO0, DO1, DO2, DO3 -# name ID w/b ins outs -TRELLIS_DPR16X4 2 0 14 4 - -#DI0 DI1 DI2 DI3 RAD0 RAD1 RAD2 RAD3 WAD0 WAD1 WAD2 WAD3 WCK WRE -- - - - 141 379 275 379 - - - - - - -- - - - 141 379 275 379 - - - - - - -- - - - 141 379 275 379 - - - - - - -- - - - 141 379 275 379 - - - - - - +# name ID w/b ins outs +$__ABC_DPR16X4_COMB 2 0 8 4 + +#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 # Box 3 : PFUMX (MUX2) # Outputs: Z |