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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 10:27:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 10:27:44 -0700 |
| commit | ca94c2d3c4785c45a2fefdb659e9ff94f2f8c7b3 (patch) | |
| tree | 1845347c4e61d7c266fd6587908e54aeccc81c33 /techlibs/common | |
| parent | 0157043b977e3b6715a6a568eb72aea247457eb0 (diff) | |
| download | yosys-ca94c2d3c4785c45a2fefdb659e9ff94f2f8c7b3.tar.gz yosys-ca94c2d3c4785c45a2fefdb659e9ff94f2f8c7b3.tar.bz2 yosys-ca94c2d3c4785c45a2fefdb659e9ff94f2f8c7b3.zip | |
Fix typo in B
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ee53701ee..da1c7c0c7 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -201,7 +201,7 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]),
.Y(partial[n-1])
);
- assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
+ assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
assign Y = partial_sum[n-1];
end
else begin
|