Add force_downto and force_upto wire attributes.

Fixes #2058.

6 files changed, 88 insertions, 23 deletions

diff --git a/techlibs/common/adff2dff.v b/techlibs/common/adff2dff.v
index 86744d415..eca0110eb 100644
--- a/techlibs/common/adff2dff.v
+++ b/techlibs/common/adff2dff.v
@@ -6,8 +6,11 @@ module adff2dff (CLK, ARST, D, Q);
 	parameter ARST_VALUE = 0;
 
 	input CLK, ARST;
+	(* force_downto *)
 	input [WIDTH-1:0] D;
+	(* force_downto *)
 	output reg [WIDTH-1:0] Q;
+	(* force_downto *)
 	wire reg [WIDTH-1:0] NEXT_Q;
 
 	wire [1023:0] _TECHMAP_DO_ = "proc;;";
diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v
index e42f346d1..a221727e7 100644
--- a/techlibs/common/cmp2lcu.v
+++ b/techlibs/common/cmp2lcu.v
@@ -12,8 +12,11 @@ parameter A_WIDTH = 0;
 parameter B_WIDTH = 0;
 parameter Y_WIDTH = 0;
 
+(* force_downto *)
 input [A_WIDTH-1:0] A;
+(* force_downto *)
 input [B_WIDTH-1:0] B;
+(* force_downto *)
 output [Y_WIDTH-1:0] Y;
 
 parameter _TECHMAP_CELLTYPE_ = "";
@@ -32,7 +35,9 @@ generate
     else begin
         // Perform sign extension on A and B
         localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
+        (* force_downto *)
         wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
+        (* force_downto *)
         wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
         // For $ge operation, start with the assumption that A and B are
         //   equal (propagating this equality if A and B turn out to be so)
@@ -54,9 +59,13 @@ parameter LCU_WIDTH = 1;
 parameter BUDGET = 0;
 parameter CI = 0;
 
+(* force_downto *)
 input [AB_WIDTH-1:0] A; // A from original $gt/$ge
+(* force_downto *)
 input [AB_WIDTH-1:0] B; // B from original $gt/$ge
+(* force_downto *)
 input [LCU_WIDTH-1:0] P; // P of $lcu
+(* force_downto *)
 input [LCU_WIDTH-1:0] G; // G of $lcu
 output Y;
 
@@ -66,6 +75,7 @@ parameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0;
 
 generate
     if (AB_WIDTH == 0) begin
+        (* force_downto *)
         wire [LCU_WIDTH-1:0] CO;
         $lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO));
         assign Y = CO[LCU_WIDTH-1];
@@ -104,8 +114,10 @@ generate
             else begin
                 // Propagate only if all pairs are equal
                 //   (inconclusive evidence to say A >= B)
+                (* force_downto *)
                 wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
                 // Generate if any comparisons call for it
+                (* force_downto *)
                 wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
             end
             if (AB_WIDTH == 1)
diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v
index 8ecd356cc..ec8f98e8d 100644
--- a/techlibs/common/cmp2lut.v
+++ b/techlibs/common/cmp2lut.v
@@ -16,8 +16,11 @@ parameter A_WIDTH = 0;
 parameter B_WIDTH = 0;
 parameter Y_WIDTH = 0;
 
+(* force_downto *)
 input [A_WIDTH-1:0] A;
+(* force_downto *)
 input [B_WIDTH-1:0] B;
+(* force_downto *)
 output [Y_WIDTH-1:0] Y;
 
 parameter _TECHMAP_CELLTYPE_ = "";
diff --git a/techlibs/common/dff2ff.v b/techlibs/common/dff2ff.v
index 2dc4d20d3..33a79ffff 100644
--- a/techlibs/common/dff2ff.v
+++ b/techlibs/common/dff2ff.v
@@ -4,7 +4,9 @@ module dff2ff (CLK, D, Q);
 	parameter CLK_POLARITY = 1;
 
 	input CLK;
+	(* force_downto *)
 	input [WIDTH-1:0] D;
+	(* force_downto *)
 	output reg [WIDTH-1:0] Q;
 
 	wire [1023:0] _TECHMAP_DO_ = "proc;;";
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 4cabb4453..bec47d01f 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -57,8 +57,11 @@ module _80_mul (A, B, Y);
 	parameter B_WIDTH = 1;

 	parameter Y_WIDTH = 1;

 

+	(* force_downto *)

 	input [A_WIDTH-1:0] A;

+	(* force_downto *)

 	input [B_WIDTH-1:0] B;

+	(* force_downto *)

 	output [Y_WIDTH-1:0] Y;

 

 	parameter _TECHMAP_CELLTYPE_ = "";

@@ -119,13 +122,19 @@ module _80_mul (A, B, Y);
 			localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);

 			localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;

 			if (A_SIGNED && B_SIGNED) begin

+				(* force_downto *)

 				wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];

+				(* force_downto *)

 				wire signed [last_Y_WIDTH-1:0] last_partial;

+				(* force_downto *)

 				wire signed [Y_WIDTH-1:0] partial_sum [n:0];

 			end

 			else begin

+				(* force_downto *)

 				wire [partial_Y_WIDTH-1:0] partial [n-1:0];

+				(* force_downto *)

 				wire [last_Y_WIDTH-1:0] last_partial;

+				(* force_downto *)

 				wire [Y_WIDTH-1:0] partial_sum [n:0];

 			end

 

@@ -170,13 +179,19 @@ module _80_mul (A, B, Y);
 			localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);

 			localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;

 			if (A_SIGNED && B_SIGNED) begin

+				(* force_downto *)

 				wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];

+				(* force_downto *)

 				wire signed [last_Y_WIDTH-1:0] last_partial;

+				(* force_downto *)

 				wire signed [Y_WIDTH-1:0] partial_sum [n:0];

 			end

 			else begin

+				(* force_downto *)

 				wire [partial_Y_WIDTH-1:0] partial [n-1:0];

+				(* force_downto *)

 				wire [last_Y_WIDTH-1:0] last_partial;

+				(* force_downto *)

 				wire [Y_WIDTH-1:0] partial_sum [n:0];

 			end

 

@@ -249,8 +264,11 @@ module _90_soft_mul (A, B, Y);
 	parameter B_WIDTH = 1;

 	parameter Y_WIDTH = 1;

 

+	(* force_downto *)

 	input [A_WIDTH-1:0] A;

+	(* force_downto *)

 	input [B_WIDTH-1:0] B;

+	(* force_downto *)

 	output [Y_WIDTH-1:0] Y;

 

 	// Indirection necessary since mapping

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 225cff449..c1efc378b 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -85,8 +85,11 @@ module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);
 	localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
 	localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
 
+	(* force_downto *)
 	input [A_WIDTH-1:0] A;
+	(* force_downto *)
 	input [B_WIDTH-1:0] B;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] Y;
 
 	localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
@@ -96,6 +99,7 @@ module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);
 	wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
 
 	integer i;
+	(* force_downto *)
 	reg [WIDTH-1:0] buffer;
 	reg overflow;
 
@@ -125,8 +129,11 @@ module _90_shift_shiftx (A, B, Y);
 	parameter B_WIDTH = 1;
 	parameter Y_WIDTH = 1;
 
+	(* force_downto *)
 	input [A_WIDTH-1:0] A;
+	(* force_downto *)
 	input [B_WIDTH-1:0] B;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] Y;
 
 	parameter _TECHMAP_CELLTYPE_ = "";
@@ -173,6 +180,7 @@ module _90_shift_shiftx (A, B, Y);
 			wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
 
 			integer i;
+			(* force_downto *)
 			reg [WIDTH-1:0] buffer;
 			reg overflow;
 
@@ -216,9 +224,12 @@ endmodule
 module _90_fa (A, B, C, X, Y);
 	parameter WIDTH = 1;
 
+	(* force_downto *)
 	input [WIDTH-1:0] A, B, C;
+	(* force_downto *)
 	output [WIDTH-1:0] X, Y;
 
+	(* force_downto *)
 	wire [WIDTH-1:0] t1, t2, t3;
 
 	assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
@@ -229,12 +240,15 @@ endmodule
 module _90_lcu (P, G, CI, CO);
 	parameter WIDTH = 2;
 
+	(* force_downto *)
 	input [WIDTH-1:0] P, G;
 	input CI;
 
+	(* force_downto *)
 	output [WIDTH-1:0] CO;
 
 	integer i, j;
+	(* force_downto *)
 	reg [WIDTH-1:0] p, g;
 
 	wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
@@ -278,38 +292,26 @@ module _90_alu (A, B, CI, BI, X, Y, CO);
 	parameter B_WIDTH = 1;
 	parameter Y_WIDTH = 1;
 
+	(* force_downto *)
 	input [A_WIDTH-1:0] A;
+	(* force_downto *)
 	input [B_WIDTH-1:0] B;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] X, Y;
 
 	input CI, BI;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] CO;
 
-	wire [Y_WIDTH-1:0] AA, BB;
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] AA = A_buf;
+	(* force_downto *)
 	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 
-	if (A_WIDTH == 0) begin
-		wire [Y_WIDTH-1:0] B_buf;
-		\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
-		assign AA = {Y_WIDTH{1'b0}};
-		assign BB = BI ? ~B_buf : B_buf;
-	end
-	else if (B_WIDTH == 0) begin
-		wire [Y_WIDTH-1:0] A_buf;
-		\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
-
-		assign AA = A_buf;
-		assign BB = {Y_WIDTH{BI ? 1'b0 : 1'b1}};
-	end
-	else begin
-		wire [Y_WIDTH-1:0] A_buf, B_buf;
-		\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
-		\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
-		assign AA = A_buf;
-		assign BB = BI ? ~B_buf : B_buf;
-	end
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 
 	\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
 
@@ -335,15 +337,19 @@ endmodule
 module \$__div_mod_u (A, B, Y, R);
 	parameter WIDTH = 1;
 
+	(* force_downto *)
 	input [WIDTH-1:0] A, B;
+	(* force_downto *)
 	output [WIDTH-1:0] Y, R;
 
+	(* force_downto *)
 	wire [WIDTH*WIDTH-1:0] chaindata;
 	assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
 
 	genvar i;
 	generate begin
 		for (i = 0; i < WIDTH; i=i+1) begin:stage
+			(* force_downto *)
 			wire [WIDTH-1:0] stage_in;
 
 			if (i == 0) begin:cp
@@ -369,14 +375,19 @@ module \$__div_mod (A, B, Y, R);
 			A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
 			B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
 
+	(* force_downto *)
 	input [A_WIDTH-1:0] A;
+	(* force_downto *)
 	input [B_WIDTH-1:0] B;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] Y, R;
 
+	(* force_downto *)
 	wire [WIDTH-1:0] A_buf, B_buf;
 	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
 	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 
+	(* force_downto *)
 	wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
 	assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
 	assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
@@ -402,8 +413,11 @@ module _90_div (A, B, Y);
 	parameter B_WIDTH = 1;
 	parameter Y_WIDTH = 1;
 
+	(* force_downto *)
 	input [A_WIDTH-1:0] A;
+	(* force_downto *)
 	input [B_WIDTH-1:0] B;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] Y;
 
 	\$__div_mod #(
@@ -427,8 +441,11 @@ module _90_mod (A, B, Y);
 	parameter B_WIDTH = 1;
 	parameter Y_WIDTH = 1;
 
+	(* force_downto *)
 	input [A_WIDTH-1:0] A;
+	(* force_downto *)
 	input [B_WIDTH-1:0] B;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] Y;
 
 	\$__div_mod #(
@@ -457,8 +474,11 @@ module _90_pow (A, B, Y);
 	parameter B_WIDTH = 1;
 	parameter Y_WIDTH = 1;
 
+	(* force_downto *)
 	input [A_WIDTH-1:0] A;
+	(* force_downto *)
 	input [B_WIDTH-1:0] B;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] Y;
 
 	wire _TECHMAP_FAIL_ = 1;
@@ -474,20 +494,27 @@ module _90_pmux (A, B, S, Y);
 	parameter WIDTH = 1;
 	parameter S_WIDTH = 1;
 
+	(* force_downto *)
 	input [WIDTH-1:0] A;
+	(* force_downto *)
 	input [WIDTH*S_WIDTH-1:0] B;
+	(* force_downto *)
 	input [S_WIDTH-1:0] S;
+	(* force_downto *)
 	output [WIDTH-1:0] Y;
 
+	(* force_downto *)
 	wire [WIDTH-1:0] Y_B;
 
 	genvar i, j;
 	generate
+		(* force_downto *)
 		wire [WIDTH*S_WIDTH-1:0] B_AND_S;
 		for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
 			assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
 		end:B_AND
 		for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
+			(* force_downto *)
 			wire [S_WIDTH-1:0] B_AND_BITS;
 			for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
 				assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];