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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 13:20:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 13:20:34 -0700 |
| commit | 915f4e34bfdf1fd2b9f97d1c15a55e2c4c49f428 (patch) | |
| tree | f06194f889ca0007153725a5f2165d10eb274920 /techlibs/common | |
| parent | fc0b5d5ab6bcbb6cc5fcacab479504c08ab80d23 (diff) | |
| download | yosys-915f4e34bfdf1fd2b9f97d1c15a55e2c4c49f428.tar.gz yosys-915f4e34bfdf1fd2b9f97d1c15a55e2c4c49f428.tar.bz2 yosys-915f4e34bfdf1fd2b9f97d1c15a55e2c4c49f428.zip | |
DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 99afce18c..5ff0e03aa 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -52,7 +52,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y;
generate
- if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)
+ if (A_SIGNED != B_SIGNED)
wire _TECHMAP_FAIL_ = 1;
// NB: A_SIGNED == B_SIGNED from here
else if (A_WIDTH < B_WIDTH)
@@ -103,10 +103,17 @@ module \$__mul (A, B, Y); genvar i;
generate
- if (A_WIDTH <= 1 || B_WIDTH <= 1)
+ if (0) begin end
+`ifdef DSP_A_MINWIDTH
+ else if (A_WIDTH < `DSP_A_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
-`ifdef DSP_MINWIDTH
- else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH)
+`endif
+`ifdef DSP_B_MINWIDTH
+ else if (B_WIDTH < `DSP_B_MINWIDTH)
+ wire _TECHMAP_FAIL_ = 1;
+`endif
+`ifdef DSP_Y_MINWIDTH
+ else if (Y_WIDTH < `DSP_Y_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
`endif
else if (A_WIDTH > `DSP_A_MAXWIDTH) begin
|