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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-01 00:03:00 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-01 00:03:00 -0700 |
| commit | f277267916b7b1c97fe90576abecde003cc231ab (patch) | |
| tree | 3e76c4069a6f8fa37e0f53f927738ed2a8665589 /techlibs/common/techmap.v | |
| parent | 736a998a75e12ca83b45b74a79e78fae8ab12d16 (diff) | |
| parent | 25533190818b0fe207be9a4626a9a273a08ae219 (diff) | |
| download | yosys-f277267916b7b1c97fe90576abecde003cc231ab.tar.gz yosys-f277267916b7b1c97fe90576abecde003cc231ab.tar.bz2 yosys-f277267916b7b1c97fe90576abecde003cc231ab.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'techlibs/common/techmap.v')
| -rw-r--r-- | techlibs/common/techmap.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index ae08c3d17..a623bb516 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -93,7 +93,7 @@ module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y); localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH); wire [1023:0] _TECHMAP_DO_00_ = "proc;;"; - wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;"; + wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;"; integer i; reg [WIDTH-1:0] buffer; @@ -136,7 +136,7 @@ module _90_shift_shiftx (A, B, Y); localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx; wire [1023:0] _TECHMAP_DO_00_ = "proc;;"; - wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_const -mux_undef -mux_bool -fine;;;"; + wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;"; integer i; reg [WIDTH-1:0] buffer; |