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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-19 14:20:04 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-19 14:20:04 -0800 |
| commit | f9af902532bcf44ddd0c5f0f28ac70880e5f2d07 (patch) | |
| tree | 057979f44068605f749b02f357c80e448d129064 /techlibs/common/simlib.v | |
| parent | 8158bc3f9930634462166aac72da96d9c9c1a5e0 (diff) | |
| parent | 2a8e5bf9535a25bba9c9c11fc7e40d5a08958d4c (diff) | |
| download | yosys-f9af902532bcf44ddd0c5f0f28ac70880e5f2d07.tar.gz yosys-f9af902532bcf44ddd0c5f0f28ac70880e5f2d07.tar.bz2 yosys-f9af902532bcf44ddd0c5f0f28ac70880e5f2d07.zip | |
Merge branch 'master' into xaig
Diffstat (limited to 'techlibs/common/simlib.v')
| -rw-r--r-- | techlibs/common/simlib.v | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index a1e0c1575..8e43fe058 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1464,11 +1464,10 @@ module \$dff (CLK, D, Q); parameter WIDTH = 0; parameter CLK_POLARITY = 1'b1; -parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}}; input CLK; input [WIDTH-1:0] D; -output reg [WIDTH-1:0] Q = INIT; +output reg [WIDTH-1:0] Q; wire pos_clk = CLK == CLK_POLARITY; always @(posedge pos_clk) begin @@ -1484,11 +1483,10 @@ module \$dffe (CLK, EN, D, Q); parameter WIDTH = 0; parameter CLK_POLARITY = 1'b1; parameter EN_POLARITY = 1'b1; -parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}}; input CLK, EN; input [WIDTH-1:0] D; -output reg [WIDTH-1:0] Q = INIT; +output reg [WIDTH-1:0] Q; wire pos_clk = CLK == CLK_POLARITY; always @(posedge pos_clk) begin @@ -1506,11 +1504,10 @@ parameter WIDTH = 0; parameter CLK_POLARITY = 1'b1; parameter SET_POLARITY = 1'b1; parameter CLR_POLARITY = 1'b1; -parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}}; input CLK; input [WIDTH-1:0] SET, CLR, D; -output reg [WIDTH-1:0] Q = INIT; +output reg [WIDTH-1:0] Q; wire pos_clk = CLK == CLK_POLARITY; wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET; @@ -1540,11 +1537,10 @@ parameter WIDTH = 0; parameter CLK_POLARITY = 1'b1; parameter ARST_POLARITY = 1'b1; parameter ARST_VALUE = 0; -parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}}; input CLK, ARST; input [WIDTH-1:0] D; -output reg [WIDTH-1:0] Q = INIT; +output reg [WIDTH-1:0] Q; wire pos_clk = CLK == CLK_POLARITY; wire pos_arst = ARST == ARST_POLARITY; @@ -1563,11 +1559,10 @@ module \$dlatch (EN, D, Q); parameter WIDTH = 0; parameter EN_POLARITY = 1'b1; -parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}}; input EN; input [WIDTH-1:0] D; -output reg [WIDTH-1:0] Q = INIT; +output reg [WIDTH-1:0] Q; always @* begin if (EN == EN_POLARITY) @@ -1585,11 +1580,10 @@ parameter WIDTH = 0; parameter EN_POLARITY = 1'b1; parameter SET_POLARITY = 1'b1; parameter CLR_POLARITY = 1'b1; -parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}}; input EN; input [WIDTH-1:0] SET, CLR, D; -output reg [WIDTH-1:0] Q = INIT; +output reg [WIDTH-1:0] Q; wire pos_en = EN == EN_POLARITY; wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET; |