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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2015-08-14 13:23:01 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 23:27:05 +0200 |
| commit | 6c00704a5ef09be46b1f05e2be477e493f37dd38 (patch) | |
| tree | a64fb142c62fd5cd49a9928b5125ea4e133f4471 /techlibs/common/simlib.v | |
| parent | 022f570563d8b067e9638bc91bbd168f4c5cb817 (diff) | |
| download | yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.tar.gz yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.tar.bz2 yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.zip | |
Another block of spelling fixes
Smaller this time
Diffstat (limited to 'techlibs/common/simlib.v')
| -rw-r--r-- | techlibs/common/simlib.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 9de71e6f9..275c469b8 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -19,7 +19,7 @@ * * The Simulation Library. * - * This verilog library contains simple simulation models for the internal + * This Verilog library contains simple simulation models for the internal * cells ($not, ...) generated by the frontends and used in most passes. * * This library can be used to verify the internal netlists as generated @@ -1163,7 +1163,7 @@ input A, EN; `ifndef SIMLIB_NOCHECKS always @* begin if (A !== 1'b1 && EN === 1'b1) begin - $display("Assertation %m failed!"); + $display("Assertion %m failed!"); $stop; end end |