aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/common/simlib.v
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2016-07-21 14:23:22 +0200
committerClifford Wolf <clifford@clifford.at>2016-07-21 14:23:22 +0200
commit5c166e76e52cdaf6ea97952c17d3d79185a59f96 (patch)
treee0f790a82816d5a148eb913b00176f4a581f5464 /techlibs/common/simlib.v
parentd7763634b68a735443c61aa32918ee0cdd6e9250 (diff)
downloadyosys-5c166e76e52cdaf6ea97952c17d3d79185a59f96.tar.gz
yosys-5c166e76e52cdaf6ea97952c17d3d79185a59f96.tar.bz2
yosys-5c166e76e52cdaf6ea97952c17d3d79185a59f96.zip
Added $initstate cell type and vlog function
Diffstat (limited to 'techlibs/common/simlib.v')
-rw-r--r--techlibs/common/simlib.v17
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 38687489a..8ab124034 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1313,6 +1313,23 @@ endmodule
// --------------------------------------------------------
+module \$initstate (Y);
+
+output reg Y = 1;
+reg [3:0] cnt = 1;
+reg trig = 0;
+
+initial trig <= 1;
+
+always @(cnt, trig) begin
+ Y <= |cnt;
+ cnt <= cnt + |cnt;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
module \$equiv (A, B, Y);
input A, B;