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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-11 16:03:19 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-15 17:17:48 +0200 |
| commit | 53ba3cf7188883a9ef1c6c506c7b3a842dccc87b (patch) | |
| tree | a974fe8ddee04385fef434ea44f53e6f4a0f0d5e /techlibs/common/simlib.v | |
| parent | 7ad8b242806357599cfcbd228cef5c331935ef7c (diff) | |
| download | yosys-53ba3cf7188883a9ef1c6c506c7b3a842dccc87b.tar.gz yosys-53ba3cf7188883a9ef1c6c506c7b3a842dccc87b.tar.bz2 yosys-53ba3cf7188883a9ef1c6c506c7b3a842dccc87b.zip | |
Fix the truth table for $_SR_* cells.
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.
Also get rid of sim-synth mismatch in the models while we're at it.
Diffstat (limited to 'techlibs/common/simlib.v')
| -rw-r--r-- | techlibs/common/simlib.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 7845a3fed..2cdddeabb 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1633,7 +1633,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR; genvar i; generate for (i = 0; i < WIDTH; i = i+1) begin:bitslices - always @(posedge pos_set[i], posedge pos_clr[i]) + always @* if (pos_clr[i]) Q[i] <= 0; else if (pos_set[i]) |