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author | Clifford Wolf <clifford@clifford.at> | 2014-07-29 14:42:33 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-29 16:35:13 +0200 |
commit | 397b00252dc0c4af725614bd12fc299147ba8efa (patch) | |
tree | e7a1dfdd61f165a517036c4efdde2c53ef9076e7 /techlibs/common/simlib.v | |
parent | 48822e79a34880c5f0b07e9889e463e7b6d7111b (diff) | |
download | yosys-397b00252dc0c4af725614bd12fc299147ba8efa.tar.gz yosys-397b00252dc0c4af725614bd12fc299147ba8efa.tar.bz2 yosys-397b00252dc0c4af725614bd12fc299147ba8efa.zip |
Added $shift and $shiftx cell types (needed for correct part select behavior)
Diffstat (limited to 'techlibs/common/simlib.v')
-rw-r--r-- | techlibs/common/simlib.v | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 1b50959c9..76aa4a52d 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -418,6 +418,54 @@ endmodule // -------------------------------------------------------- +module \$shift (A, B, Y); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; + +input [A_WIDTH-1:0] A; +input [B_WIDTH-1:0] B; +output [Y_WIDTH-1:0] Y; + +generate + if (B_SIGNED) begin:BLOCK1 + assign Y = $signed(B) < 0 ? A << -B : A >> B; + end else begin:BLOCK2 + assign Y = A >> B; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + +module \$shiftx (A, B, Y); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; + +input [A_WIDTH-1:0] A; +input [B_WIDTH-1:0] B; +output [Y_WIDTH-1:0] Y; + +generate + if (B_SIGNED) begin:BLOCK1 + assign Y = A[$signed(B) +: Y_WIDTH]; + end else begin:BLOCK2 + assign Y = A[B +: Y_WIDTH]; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + module \$lt (A, B, Y); parameter A_SIGNED = 0; |