diff options
| author | Ahmed Irfan <irfan@levert.(none)> | 2015-04-03 16:38:07 +0200 |
|---|---|---|
| committer | Ahmed Irfan <irfan@levert.(none)> | 2015-04-03 16:38:07 +0200 |
| commit | bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee (patch) | |
| tree | 1d02541701054a1c3b1cdb66478d0cbc31c2d38f /techlibs/common/simcells.v | |
| parent | 8acdd90bc918b780ad45cdac42b3baf84d2cc476 (diff) | |
| parent | 4b4490761949e738dee54bdfc52e080e0a5c9067 (diff) | |
| download | yosys-bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee.tar.gz yosys-bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee.tar.bz2 yosys-bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee.zip | |
Merge branch 'master' of https://github.com/cliffordwolf/yosys
Diffstat (limited to 'techlibs/common/simcells.v')
| -rw-r--r-- | techlibs/common/simcells.v | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index a2a377350..eb62d7830 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -25,6 +25,12 @@ * */ +module \$_BUF_ (A, Y); +input A; +output Y; +assign Y = A; +endmodule + module \$_NOT_ (A, Y); input A; output Y; @@ -157,6 +163,38 @@ always @(posedge C) begin end endmodule +module \$_DFFE_NN_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(negedge C) begin + if (!E) Q <= D; +end +endmodule + +module \$_DFFE_NP_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(negedge C) begin + if (E) Q <= D; +end +endmodule + +module \$_DFFE_PN_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(posedge C) begin + if (!E) Q <= D; +end +endmodule + +module \$_DFFE_PP_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(posedge C) begin + if (E) Q <= D; +end +endmodule + module \$_DFF_NN0_ (D, Q, C, R); input D, C, R; output reg Q; |