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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-01 10:01:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-01 10:01:54 +0200 |
| commit | 6bbe2fdbf32e6335cdbecc21547e54992c3a606d (patch) | |
| tree | 7ce91013e7b348d059f6c87e3aad62f6b1b0fbd6 /techlibs/common/simcells.v | |
| parent | 3b6a02d3a74dc0113d595c6d26a4436160e28a6f (diff) | |
| download | yosys-6bbe2fdbf32e6335cdbecc21547e54992c3a606d.tar.gz yosys-6bbe2fdbf32e6335cdbecc21547e54992c3a606d.tar.bz2 yosys-6bbe2fdbf32e6335cdbecc21547e54992c3a606d.zip | |
Add splitcmplxassign test case and silence splitcmplxassign warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/common/simcells.v')
0 files changed, 0 insertions, 0 deletions