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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
| commit | 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (patch) | |
| tree | d1a4bb9dfe62ac911ca4751a98b3b63dba22af40 /techlibs/common/simcells.v | |
| parent | 6ca0c569d92883b6eac1725204de90aee4af31bc (diff) | |
| download | yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.gz yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.bz2 yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.zip | |
Renamed "stdcells.v" to "techmap.v"
Diffstat (limited to 'techlibs/common/simcells.v')
| -rw-r--r-- | techlibs/common/simcells.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 5ecec7891..d492c2f15 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -21,7 +21,7 @@ * * This verilog library contains simple simulation models for the internal * logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology - * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass. + * mapper (see "techmap.v" in this directory) and expected by the "abc" pass. * */ |