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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-10-01 11:04:32 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-01 11:04:32 +0300 |
| commit | e092c4ae6b60cf67efd16efbfbf739895ad501c0 (patch) | |
| tree | 939a5b94d14a11df511aa95482458b33a1f6139f /techlibs/anlogic | |
| parent | 1070f2e90b9ba37856932189ef09a0f2316d9a21 (diff) | |
| parent | d963e8c2c6207ad98d48dc528922ad58c030173f (diff) | |
| download | yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.tar.gz yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.tar.bz2 yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.zip | |
Merge branch 'master' into SergeyDegtyar/efinix
Diffstat (limited to 'techlibs/anlogic')
| -rw-r--r-- | techlibs/anlogic/cells_sim.v | 99 |
1 files changed, 94 insertions, 5 deletions
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v index 058e76605..0fba43572 100644 --- a/techlibs/anlogic/cells_sim.v +++ b/techlibs/anlogic/cells_sim.v @@ -1,5 +1,5 @@ module AL_MAP_SEQ ( - output q, + output reg q, input ce, input clk, input sr, @@ -9,6 +9,71 @@ module AL_MAP_SEQ ( parameter REGSET = "RESET"; //RESET/SET parameter SRMUX = "SR"; //SR/INV parameter SRMODE = "SYNC"; //SYNC/ASYNC + + wire clk_ce; + assign clk_ce = ce ? clk : 1'b0; + + wire srmux; + generate + case (SRMUX) + "SR": assign srmux = sr; + "INV": assign srmux = ~sr; + default: assign srmux = sr; + endcase + endgenerate + + wire regset; + generate + case (REGSET) + "RESET": assign regset = 1'b0; + "SET": assign regset = 1'b1; + default: assign regset = 1'b0; + endcase + endgenerate + + initial q = regset; + + generate + if (DFFMODE == "FF") + begin + if (SRMODE == "ASYNC") + begin + always @(posedge clk_ce, posedge srmux) + if (srmux) + q <= regset; + else + q <= d; + end + else + begin + always @(posedge clk_ce) + if (srmux) + q <= regset; + else + q <= d; + end + end + else + begin + // DFFMODE == "LATCH" + if (SRMODE == "ASYNC") + begin + always @(clk_ce, srmux) + if (srmux) + q <= regset; + else + q <= d; + end + else + begin + always @(clk_ce) + if (srmux) + q <= regset; + else + q <= d; + end + end + endgenerate endmodule module AL_MAP_LUT1 ( @@ -17,7 +82,8 @@ module AL_MAP_LUT1 ( ); parameter [1:0] INIT = 2'h0; parameter EQN = "(A)"; - assign o = INIT >> a; + + assign o = a ? INIT[1] : INIT[0]; endmodule module AL_MAP_LUT2 ( @@ -27,7 +93,9 @@ module AL_MAP_LUT2 ( ); parameter [3:0] INIT = 4'h0; parameter EQN = "(A)"; - assign o = INIT >> {b, a}; + + wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT3 ( @@ -38,7 +106,10 @@ module AL_MAP_LUT3 ( ); parameter [7:0] INIT = 8'h0; parameter EQN = "(A)"; - assign o = INIT >> {c, b, a}; + + wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0]; + wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT4 ( @@ -50,7 +121,11 @@ module AL_MAP_LUT4 ( ); parameter [15:0] INIT = 16'h0; parameter EQN = "(A)"; - assign o = INIT >> {d, c, b, a}; + + wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0]; + wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT5 ( @@ -100,4 +175,18 @@ module AL_MAP_ADDER ( output [1:0] o ); parameter ALUTYPE = "ADD"; + + generate + case (ALUTYPE) + "ADD": assign o = a + b + c; + "SUB": assign o = a - b - c; + "A_LE_B": assign o = a - b - c; + + "ADD_CARRY": assign o = { a, 1'b0 }; + "SUB_CARRY": assign o = { ~a, 1'b0 }; + "A_LE_B_CARRY": assign o = { a, 1'b0 }; + default: assign o = a + b + c; + endcase + endgenerate + endmodule |