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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:00:50 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:00:50 -0700 |
commit | 6872805a3eb738a0a5921b232022abfd507cebb8 (patch) | |
tree | b871344e8f96cd30c5a6bc3f275476e30f792de0 /techlibs/anlogic/synth_anlogic.cc | |
parent | 6b51c154c6812f58676402ebbbdbb18d053ca4be (diff) | |
parent | bb2d5bc4f85ac95104fbd2591ad92ebf0c22e11d (diff) | |
download | yosys-6872805a3eb738a0a5921b232022abfd507cebb8.tar.gz yosys-6872805a3eb738a0a5921b232022abfd507cebb8.tar.bz2 yosys-6872805a3eb738a0a5921b232022abfd507cebb8.zip |
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
-rw-r--r-- | techlibs/anlogic/synth_anlogic.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 620bf3965..b87fc8566 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -154,7 +154,7 @@ struct SynthAnlogicPass : public ScriptPass { run("memory_bram -rules +/anlogic/drams.txt"); run("techmap -map +/anlogic/drams_map.v"); - run("anlogic_determine_init"); + run("setundef -zero -params t:EG_LOGIC_DRAM16X4"); } if (check_label("fine")) @@ -186,6 +186,11 @@ struct SynthAnlogicPass : public ScriptPass { run("techmap -map +/anlogic/cells_map.v"); run("clean"); + } + + if (check_label("map_anlogic")) + { + run("anlogic_fixcarry"); run("anlogic_eqn"); } |