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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-22 18:09:10 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-22 18:09:10 +0200 |
| commit | 2c8c8b3c74ccc630e56c412a83fa60fb7066fb4d (patch) | |
| tree | 95a650ffaadbce982b0801ef0e782e1f193992cc /techlibs/anlogic/synth_anlogic.cc | |
| parent | 4c449caf9bb7a855b8e61cb96f99f59141ea6ef5 (diff) | |
| parent | 4a32e29445f65edd1726808a7353a9d0e2560c00 (diff) | |
| download | yosys-2c8c8b3c74ccc630e56c412a83fa60fb7066fb4d.tar.gz yosys-2c8c8b3c74ccc630e56c412a83fa60fb7066fb4d.tar.bz2 yosys-2c8c8b3c74ccc630e56c412a83fa60fb7066fb4d.zip | |
Merge pull request #1289 from mmicko/anlogic_fixes
Anlogic fixes and optimization
Diffstat (limited to 'techlibs/anlogic/synth_anlogic.cc')
| -rw-r--r-- | techlibs/anlogic/synth_anlogic.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 620bf3965..b87fc8566 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -154,7 +154,7 @@ struct SynthAnlogicPass : public ScriptPass { run("memory_bram -rules +/anlogic/drams.txt"); run("techmap -map +/anlogic/drams_map.v"); - run("anlogic_determine_init"); + run("setundef -zero -params t:EG_LOGIC_DRAM16X4"); } if (check_label("fine")) @@ -186,6 +186,11 @@ struct SynthAnlogicPass : public ScriptPass { run("techmap -map +/anlogic/cells_map.v"); run("clean"); + } + + if (check_label("map_anlogic")) + { + run("anlogic_fixcarry"); run("anlogic_eqn"); } |