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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-11 12:43:46 -0800 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-11 12:43:46 -0800 |
| commit | 311396860b7380e5dc68e66c17d5083d1953fe3f (patch) | |
| tree | c5146a20e59acc342dfe414e1b35fdfe419b9e81 /techlibs/anlogic/drams_map.v | |
| parent | 76696e80041dc5b8f4ba986f4f83d6e7b6854e96 (diff) | |
| parent | e112d2fbf5a31f00ef19e6d05f28fecc1e9c56b9 (diff) | |
| download | yosys-311396860b7380e5dc68e66c17d5083d1953fe3f.tar.gz yosys-311396860b7380e5dc68e66c17d5083d1953fe3f.tar.bz2 yosys-311396860b7380e5dc68e66c17d5083d1953fe3f.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'techlibs/anlogic/drams_map.v')
| -rw-r--r-- | techlibs/anlogic/drams_map.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v index 87cbb6a45..084e2a25f 100644 --- a/techlibs/anlogic/drams_map.v +++ b/techlibs/anlogic/drams_map.v @@ -1,4 +1,5 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0]INIT = 64'bx; input CLK1; input [3:0] A1ADDR; @@ -8,7 +9,9 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [3:0] B1DATA; input B1EN; - EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ ( + EG_LOGIC_DRAM16X4 #( + `include "dram_init_16x4.vh" + ) _TECHMAP_REPLACE_ ( .di(B1DATA), .waddr(B1ADDR), .wclk(CLK1), |