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| author | Benedikt Tutzer <benedikt.tutzer@tuwien.ac.at> | 2019-03-28 12:16:39 +0100 |
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| committer | Benedikt Tutzer <benedikt.tutzer@tuwien.ac.at> | 2019-03-28 12:16:39 +0100 |
| commit | 03d1606b42110f8eac7311ac57c7334d1f781273 (patch) | |
| tree | 9fc490a93fbb75ac3e23b276a151e22ca1a3b84e /techlibs/anlogic/drams_map.v | |
| parent | b9288b216dce110ad11eb0615a6a911a9fcae05b (diff) | |
| parent | 32bd0f22ec93202e67395901cdc64c20df7f0da7 (diff) | |
| download | yosys-03d1606b42110f8eac7311ac57c7334d1f781273.tar.gz yosys-03d1606b42110f8eac7311ac57c7334d1f781273.tar.bz2 yosys-03d1606b42110f8eac7311ac57c7334d1f781273.zip | |
Merge remote-tracking branch 'origin/master' into feature/python_bindings
Diffstat (limited to 'techlibs/anlogic/drams_map.v')
| -rw-r--r-- | techlibs/anlogic/drams_map.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v new file mode 100644 index 000000000..084e2a25f --- /dev/null +++ b/techlibs/anlogic/drams_map.v @@ -0,0 +1,22 @@ +module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0]INIT = 64'bx; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + EG_LOGIC_DRAM16X4 #( + `include "dram_init_16x4.vh" + ) _TECHMAP_REPLACE_ ( + .di(B1DATA), + .waddr(B1ADDR), + .wclk(CLK1), + .we(B1EN), + .raddr(A1ADDR), + .do(A1DATA) + ); +endmodule |