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authorEddie Hung <eddie@fpgeh.com>2019-08-16 16:51:22 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-16 16:51:22 -0700
commit24c934f1af3859fe64ff4fb87a2a3de97695cde4 (patch)
tree131c64cee5a0cf09adc68b32f25e06a9da668ad0 /techlibs/anlogic/anlogic_determine_init.cc
parent1c9f3fadb9f60653fc9d1d7d72ba22033e077468 (diff)
parent5abe133323b2a6a46959f796c4730b2d70cdea26 (diff)
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Merge branch 'eddie/abc9_refactor' into xaig_dff
Diffstat (limited to 'techlibs/anlogic/anlogic_determine_init.cc')
-rw-r--r--techlibs/anlogic/anlogic_determine_init.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
index 34b1d4f8a..c4089dac2 100644
--- a/techlibs/anlogic/anlogic_determine_init.cc
+++ b/techlibs/anlogic/anlogic_determine_init.cc
@@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass {
extra_args(args, args.size(), design);
- size_t cnt = 0;
+ int cnt = 0;
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass {
}
}
}
- log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+ log_header(design, "Updated %d cells with determined init value.\n", cnt);
}
} AnlogicDetermineInitPass;