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author | Clifford Wolf <clifford@clifford.at> | 2015-04-18 09:29:03 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-04-18 09:29:03 +0200 |
commit | faa95dd8455a87726f1612c32383675c24fcfcb7 (patch) | |
tree | bfd9dec3f77ebe04262b1eea9be5385befb4bf05 /passes | |
parent | 9041f34233a0bfeb10f98bbbed297614487c2d11 (diff) | |
download | yosys-faa95dd8455a87726f1612c32383675c24fcfcb7.tar.gz yosys-faa95dd8455a87726f1612c32383675c24fcfcb7.tar.bz2 yosys-faa95dd8455a87726f1612c32383675c24fcfcb7.zip |
don't consider blackbox modules in "sat" command
Diffstat (limited to 'passes')
-rw-r--r-- | passes/sat/sat.cc | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 9e5cc9e91..a420011ec 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1293,13 +1293,11 @@ struct SatPass : public Pass { extra_args(args, argidx, design); RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) { - if (module) - log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", - RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first)); - module = mod_it.second; - } + for (auto mod : design->selected_modules()) { + if (module) + log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", log_id(module), log_id(mod)); + module = mod; + } if (module == NULL) log_cmd_error("Can't perform SAT on an empty selection!\n"); |