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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 16:20:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 16:20:43 -0700 |
| commit | f587950bde58b326e1f7319c84d5652a0dc43216 (patch) | |
| tree | 8c4124877720110be551d94e433dc5a4259be913 /passes | |
| parent | b15b410b41cca3a79bfcfc9c91f665815f31ab5b (diff) | |
| download | yosys-f587950bde58b326e1f7319c84d5652a0dc43216.tar.gz yosys-f587950bde58b326e1f7319c84d5652a0dc43216.tar.bz2 yosys-f587950bde58b326e1f7319c84d5652a0dc43216.zip | |
More unused
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/pmux2shiftx.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/passes/techmap/pmux2shiftx.cc b/passes/techmap/pmux2shiftx.cc index 08cb06d5f..f8cdf5783 100644 --- a/passes/techmap/pmux2shiftx.cc +++ b/passes/techmap/pmux2shiftx.cc @@ -62,7 +62,6 @@ struct Pmux2ShiftxPass : public Pass { shiftx_a.append(cell->getPort("\\A")); pmux_s.append(module->Not(NEW_ID, module->ReduceOr(NEW_ID, cell->getPort("\\S")))); } - const int width = cell->getParam("\\WIDTH").as_int(); const int clog2width = ceil(log2(s_width)); RTLIL::SigSpec pmux_b; |