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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-09 09:48:29 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-09 09:48:29 +0100 |
| commit | f37ac5d934e76c12d7412451d45ded7a7df04b82 (patch) | |
| tree | b5783251c8b80f954dfa169ceec819bf96631e48 /passes | |
| parent | ede348cdc285f4b4f1c53942d515a7082e53e37a (diff) | |
| download | yosys-f37ac5d934e76c12d7412451d45ded7a7df04b82.tar.gz yosys-f37ac5d934e76c12d7412451d45ded7a7df04b82.tar.bz2 yosys-f37ac5d934e76c12d7412451d45ded7a7df04b82.zip | |
Fixes and error check
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/sim.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index d7f4de507..79140e615 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1095,6 +1095,8 @@ struct SimWorker : SimShared void run_cosim_aiger_witness(Module *topmod) { log_assert(top == nullptr); + if ((clock.size()+clockn.size())==0) + log_error("Clock signal must be specified.\n"); std::ifstream mf(map_filename); std::string type, symbol; int variable, index; @@ -1213,6 +1215,8 @@ struct SimWorker : SimShared void run_cosim_btor2_witness(Module *topmod) { log_assert(top == nullptr); + if ((clock.size()+clockn.size())==0) + log_error("Clock signal must be specified.\n"); std::ifstream f; f.open(sim_filename.c_str()); if (f.fail() || GetSize(sim_filename) == 0) @@ -1278,7 +1282,7 @@ struct SimWorker : SimShared if ((int)parts[1].size() != w->width) log_error("Size of wire %s is different than provided data.\n", log_signal(w)); - top->set_state(w, Const(parts[1])); + top->set_state(w, Const::from_string(parts[1])); break; } } |