diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-06-01 11:57:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-06-01 11:57:28 +0200 |
| commit | f273291dfe5de460192ef2a63a121b3c2e8b9a62 (patch) | |
| tree | 38c2e35a1f30e64f5c186b051b3d385d2e84ae18 /passes | |
| parent | 4cd6d5556ade3a6da64d3639e6b6e547222820e8 (diff) | |
| download | yosys-f273291dfe5de460192ef2a63a121b3c2e8b9a62.tar.gz yosys-f273291dfe5de460192ef2a63a121b3c2e8b9a62.tar.bz2 yosys-f273291dfe5de460192ef2a63a121b3c2e8b9a62.zip | |
Add setundef -anyseq / -anyconst support to -undriven mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/setundef.cc | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index be26c3fd4..3a3ebedf1 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -176,7 +176,10 @@ struct SetundefPass : public Pass { extra_args(args, argidx, design); if (!got_value) - log_cmd_error("One of the options -zero, -one, -anyseq, or -random <seed> must be specified.\n"); + log_cmd_error("One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified.\n"); + + if (init_mode && (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)) + log_cmd_error("The options -init and -anyseq / -anyconst are exclusive.\n"); for (auto module : design->selected_modules()) { @@ -204,8 +207,13 @@ struct SetundefPass : public Pass { RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; - for (int i = 0; i < c.width; i++) - bits.append(worker.next_bit()); + if (worker.next_bit_mode == MODE_ANYSEQ) + bits = module->Anyseq(NEW_ID, c.width); + else if (worker.next_bit_mode == MODE_ANYCONST) + bits = module->Anyconst(NEW_ID, c.width); + else + for (int i = 0; i < c.width; i++) + bits.append(worker.next_bit()); module->connect(RTLIL::SigSig(c, bits)); } } |