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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 12:03:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 12:03:25 -0700 |
| commit | d88903e6108f8afc8e74ee3d3e942b98c21e1ae9 (patch) | |
| tree | 3592ef55884724a896a3f7fba2a5b75a954a52ff /passes | |
| parent | 1809f463fb235a5e4c137ee992712ecc8d235fdc (diff) | |
| download | yosys-d88903e6108f8afc8e74ee3d3e942b98c21e1ae9.tar.gz yosys-d88903e6108f8afc8e74ee3d3e942b98c21e1ae9.tar.bz2 yosys-d88903e6108f8afc8e74ee3d3e942b98c21e1ae9.zip | |
Cleanup xilinx_dsp
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 0ee230ccc..7d34c6a78 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -2,7 +2,7 @@ pattern xilinx_dsp_pack udata <std::function<SigSpec(const SigSpec&)>> unextend state <SigBit> clock -state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP +state <SigSpec> sigA sigB sigC sigD sigM sigP state <IdString> postAddAB postAddMuxAB state <bool> ffA1cepol ffA2cepol ffADcepol ffB1cepol ffB2cepol ffCcepol ffDcepol ffMcepol ffPcepol state <bool> ffArstpol ffADrstpol ffBrstpol ffCrstpol ffDrstpol ffMrstpol ffPrstpol |