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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-10 08:48:20 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-10 08:48:20 +0200 |
| commit | c66b4b9131bb663ab5cd597635ba74068bd69fe6 (patch) | |
| tree | a75749a639324a27f32cad4c6929ece64d96fa72 /passes | |
| parent | 27b27b8781ab8d57aa85a432aba7e914570feffb (diff) | |
| parent | 9546ccdbd348b1dc056884a536246801cdf1c4f1 (diff) | |
| download | yosys-c66b4b9131bb663ab5cd597635ba74068bd69fe6.tar.gz yosys-c66b4b9131bb663ab5cd597635ba74068bd69fe6.tar.bz2 yosys-c66b4b9131bb663ab5cd597635ba74068bd69fe6.zip | |
Merge pull request #1177 from YosysHQ/clifford/async
Fix clk2fflogic adff reset semantic to negative hold time on reset
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 49ec795d3..4bb4aa047 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -253,6 +253,13 @@ struct Clk2fflogicPass : public Pass { SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); Const rstval = cell->parameters["\\ARST_VALUE"]; + Wire *past_arst = module->addWire(NEW_ID); + module->addFf(NEW_ID, arst, past_arst); + if (cell->parameters["\\ARST_POLARITY"].as_bool()) + arst = module->LogicOr(NEW_ID, arst, past_arst); + else + arst = module->LogicAnd(NEW_ID, arst, past_arst); + if (cell->parameters["\\ARST_POLARITY"].as_bool()) module->addMux(NEW_ID, qval, rstval, arst, sig_q); else |