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| author | Clifford Wolf <clifford@clifford.at> | 2013-04-13 21:18:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-04-13 21:18:24 +0200 |
| commit | c6198ea5a833008789ecbc9cc4da3ab61fcf4e82 (patch) | |
| tree | dd896a060e12e3f7cc7b0fd34990754b5394669a /passes | |
| parent | db10275251ca92bf71dd1e0dca25327cc89259e4 (diff) | |
| download | yosys-c6198ea5a833008789ecbc9cc4da3ab61fcf4e82.tar.gz yosys-c6198ea5a833008789ecbc9cc4da3ab61fcf4e82.tar.bz2 yosys-c6198ea5a833008789ecbc9cc4da3ab61fcf4e82.zip | |
Fixed a bug in opt_const when optimizing 1-bit compares with constants
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_const.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 0effd964b..7c82f0fcb 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -181,8 +181,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); if (a.is_fully_const()) { - RTLIL::SigSpec tmp = a; - a = b, b = tmp; + RTLIL::SigSpec tmp; + tmp = a, a = b, b = tmp; + cell->connections["\\A"] = a; + cell->connections["\\B"] = b; } if (b.is_fully_const()) { |