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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-03 12:34:18 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-03 12:34:18 +0100 |
| commit | c3e9f0712fa2a35cf3e4a638164aed7ab8d8ff4a (patch) | |
| tree | d42896f5540da347980e208f895f9a5983042e38 /passes | |
| parent | 914e208aa3b6d52d3a4145525d15c4fba237fd87 (diff) | |
| download | yosys-c3e9f0712fa2a35cf3e4a638164aed7ab8d8ff4a.tar.gz yosys-c3e9f0712fa2a35cf3e4a638164aed7ab8d8ff4a.tar.bz2 yosys-c3e9f0712fa2a35cf3e4a638164aed7ab8d8ff4a.zip | |
Another small freduce cleanup/bugfix
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/freduce.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index cc3739fe4..4db11436e 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -482,7 +482,8 @@ struct FreduceWorker RTLIL::Cell *drv = drivers.at(grp[i].bit).first; RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID); for (auto &port : drv->connections) - sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); + if (ct.cell_output(drv->type, port.first)) + sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); if (grp[i].inverted) { |