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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 10:32:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 10:32:01 -0700 |
| commit | bd8661e0247121cf411b4c35fcedbc12a5919b50 (patch) | |
| tree | 3526963e4aa9bbe35f48e300ba9f2ed047c6d67e /passes | |
| parent | c0bb1d22e81b935e90032ed886e58787b3e61df5 (diff) | |
| download | yosys-bd8661e0247121cf411b4c35fcedbc12a5919b50.tar.gz yosys-bd8661e0247121cf411b4c35fcedbc12a5919b50.tar.bz2 yosys-bd8661e0247121cf411b4c35fcedbc12a5919b50.zip | |
CREG to check for \keep
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_CREG.pmg | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index d79abdd4a..a31dc80bf 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -87,6 +87,9 @@ code reject; if (c.wire->get_bool_attribute(\keep)) reject; + Const init = c.wire->attributes.at(\init, State::Sx); + if (!init.is_fully_undef() && !init.is_fully_zero()) + reject; } endcode |