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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-08 19:06:16 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-08 19:06:16 +0100 |
| commit | bcd8a2fc567e0bbc1b04467ac7a3b32ed332f7f3 (patch) | |
| tree | ee6ea78258f5e379c878f5ecd910b6d7fac386dd /passes | |
| parent | 09ee65a050ffc8fe1a208140cce32a6a5f15c4ab (diff) | |
| download | yosys-bcd8a2fc567e0bbc1b04467ac7a3b32ed332f7f3.tar.gz yosys-bcd8a2fc567e0bbc1b04467ac7a3b32ed332f7f3.tar.bz2 yosys-bcd8a2fc567e0bbc1b04467ac7a3b32ed332f7f3.zip | |
Fixed eval_select_op() api
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/select.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index f8cfa9ced..247765f0d 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -839,7 +839,7 @@ RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *des } // extern decl. in register.h -void eval_select_op(vector<RTLIL::Selection> &work, string &op, RTLIL::Design *design) +void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design) { work_stack.swap(work); select_stmt(design, op); |