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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 11:49:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-13 13:16:49 -0700 |
| commit | b97a9cd3f3619f035af4792de199298487c689a9 (patch) | |
| tree | 422ce7b381f1b3639515344721bd6789cb7550af /passes | |
| parent | 840bb170896c1acbbd321c4214df1f3b15108466 (diff) | |
| download | yosys-b97a9cd3f3619f035af4792de199298487c689a9.tar.gz yosys-b97a9cd3f3619f035af4792de199298487c689a9.tar.bz2 yosys-b97a9cd3f3619f035af4792de199298487c689a9.zip | |
Supress error for unhandled \init if whole module selected
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/zinit.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index a427c4987..5cfc82ac9 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -141,9 +141,10 @@ struct ZinitPass : public Pass { cell->setPort(ID::Q, initwire); } - for (auto &it : initbits) - if (donebits.count(it.first) == 0) - log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second)); + if (!design->selected_whole_module(module)) + for (auto &it : initbits) + if (donebits.count(it.first) == 0) + log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second)); } } } ZinitPass; |