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author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-06-13 05:26:30 +0000 |
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committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-06-13 05:26:30 +0000 |
commit | b70de98bd1a3141ee56ff991c5bfd6e584cb25e3 (patch) | |
tree | 0d0e69be93bf5c89b93864bbef4a7c17da35b418 /passes | |
parent | 2139a5c21a9a20b6a5c254bd2f7c09ea29fdaf3d (diff) | |
download | yosys-b70de98bd1a3141ee56ff991c5bfd6e584cb25e3.tar.gz yosys-b70de98bd1a3141ee56ff991c5bfd6e584cb25e3.tar.bz2 yosys-b70de98bd1a3141ee56ff991c5bfd6e584cb25e3.zip |
splitnets: Slightly improve efficiency by avoiding some unnecessary lookups
Diffstat (limited to 'passes')
-rw-r--r-- | passes/cmds/splitnets.cc | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index de275874f..8d5cd2034 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -61,20 +61,24 @@ struct SplitnetsWorker new_wire->port_output = wire->port_output; new_wire->start_offset = wire->start_offset + offset; - if (wire->attributes.count(ID::src)) - new_wire->attributes[ID::src] = wire->attributes.at(ID::src); + auto it = wire->attributes.find(ID::src); + if (it != wire->attributes.end()) + new_wire->attributes.emplace(ID::src, it->second); - if (wire->attributes.count(ID::hdlname)) - new_wire->attributes[ID::hdlname] = wire->attributes.at(ID::hdlname); + it = wire->attributes.find(ID::hdlname); + if (it != wire->attributes.end()) + new_wire->attributes.emplace(ID::hdlname, it->second); - if (wire->attributes.count(ID::keep)) - new_wire->attributes[ID::keep] = wire->attributes.at(ID::keep); + it = wire->attributes.find(ID::keep); + if (it != wire->attributes.end()) + new_wire->attributes.emplace(ID::keep, it->second); - if (wire->attributes.count(ID::init)) { - Const old_init = wire->attributes.at(ID::init), new_init; + it = wire->attributes.find(ID::init); + if (it != wire->attributes.end()) { + Const old_init = it->second, new_init; for (int i = offset; i < offset+width; i++) new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx); - new_wire->attributes[ID::init] = new_init; + new_wire->attributes.emplace(ID::init, new_init); } std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector(); |