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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 22:12:41 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-22 22:12:41 -0700 |
| commit | b700592881a2f2a87cca9776cd9bfca85781c9ec (patch) | |
| tree | 559ae8593ad3a6ab35b756c68606f44bcb046a2c /passes | |
| parent | fa9df06c9dc5ead43645ba973e2ca8c63adfb29d (diff) | |
| parent | 51ae0f4e20815df98204b72bd740c00f5f2a1197 (diff) | |
| download | yosys-b700592881a2f2a87cca9776cd9bfca85781c9ec.tar.gz yosys-b700592881a2f2a87cca9776cd9bfca85781c9ec.tar.bz2 yosys-b700592881a2f2a87cca9776cd9bfca85781c9ec.zip | |
Merge pull request #1984 from YosysHQ/eddie/getParam_exception
kernel: Cell::getParam() to throw exception again if not found
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_cascade.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index a36edd9e5..8babb88e6 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -188,7 +188,7 @@ arg next // driven by the 'P' output of the previous DSP cell, and (c) has its // 'PCIN' port unused match nextP - select !param(nextP, \CREG).as_bool() + select !nextP->type.in(\DSP48E1) || !param(nextP, \CREG).as_bool() select (nextP->type.in(\DSP48A, \DSP48A1) && port(nextP, \OPMODE, Const(0, 8)).extract(2,2) == Const::from_string("11")) || (nextP->type.in(\DSP48E1) && port(nextP, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")) select nusers(port(nextP, \C, SigSpec())) > 1 select nusers(port(nextP, \PCIN, SigSpec())) == 0 |