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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-21 11:52:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-21 11:54:00 +0200 |
| commit | b66bf8bed17473b0b972671fe3c4f4c5d147e68a (patch) | |
| tree | 53ec655f2ab4a7a6c07dd2861124b2179cca97ce /passes | |
| parent | 11c27b5e69fc74ff147309e550b67fd9cddb5f80 (diff) | |
| download | yosys-b66bf8bed17473b0b972671fe3c4f4c5d147e68a.tar.gz yosys-b66bf8bed17473b0b972671fe3c4f4c5d147e68a.tar.bz2 yosys-b66bf8bed17473b0b972671fe3c4f4c5d147e68a.zip | |
Do not detect fsm state registers with init attribute
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index fd0ae44b9..740113e35 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -110,6 +110,8 @@ static bool check_state_users(RTLIL::SigSpec sig) static void detect_fsm(RTLIL::Wire *wire) { + if (wire->attributes.count("\\init") > 0) + return; if (wire->attributes.count("\\fsm_encoding") > 0 || wire->width <= 1) return; if (sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)))) |