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| author | Clifford Wolf <clifford@clifford.at> | 2013-02-28 13:59:49 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-02-28 13:59:49 +0100 |
| commit | af561800edc1d98c33fe057d5c02898460c9d6b9 (patch) | |
| tree | bcfb0dce925ce7ab6b3c6dc6d0fe460431b47c77 /passes | |
| parent | 6ac41b2bb1d41328eb91c2622d8f70cb43a60f0f (diff) | |
| download | yosys-af561800edc1d98c33fe057d5c02898460c9d6b9.tar.gz yosys-af561800edc1d98c33fe057d5c02898460c9d6b9.tar.bz2 yosys-af561800edc1d98c33fe057d5c02898460c9d6b9.zip | |
Added online help for "show" and "hierarchy" commands
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 28 |
1 files changed, 25 insertions, 3 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index c8cd77a16..9ba1594df 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -139,7 +139,30 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top) } struct HierarchyPass : public Pass { - HierarchyPass() : Pass("hierarchy") { } + HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" hierarchy [-check] [-top <module>]\n"); + log("\n"); + log("In parametric designs, a module might exists in serveral variations with\n"); + log("different parameter values. This pass looks at all modules in the current\n"); + log("design an re-runs the language frontends for the parametric modules as\n"); + log("needed.\n"); + log("\n"); + log(" -check\n"); + log(" also check the design hierarchy. this generates an error when\n"); + log(" an unknown module is used as cell type.\n"); + log("\n"); + log(" -top <module>\n"); + log(" use the specified top module to built a design hierarchy. modules\n"); + log(" outside this tree (unused modules) are removed.\n"); + log("\n"); + log("This pass ignores the current selection and always operates on all modules\n"); + log("in the current design.\n"); + log("\n"); + } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing HIERARCHY pass (removing modules outside design hierarchy).\n"); @@ -165,9 +188,8 @@ struct HierarchyPass : public Pass { log_cmd_error("Module `%s' not found!\n", args[argidx].c_str()); continue; } - break; + log_cmd_error("Unkown option %s.\n", args[argidx].c_str()); } - extra_args(args, argidx, design); if (top_mod != NULL) hierarchy(design, top_mod); |