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| author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:44:47 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:44:47 +0100 |
| commit | a7988c01af4bab7390c60fdde04b92ed816aa306 (patch) | |
| tree | 2e480ecaa6905125ba11e46af9f74ac41c5432eb /passes | |
| parent | 9c955c4c17fe16e43677304372417637ac733bd0 (diff) | |
| download | yosys-a7988c01af4bab7390c60fdde04b92ed816aa306.tar.gz yosys-a7988c01af4bab7390c60fdde04b92ed816aa306.tar.bz2 yosys-a7988c01af4bab7390c60fdde04b92ed816aa306.zip | |
Copy attributes from state signal to fsm cell
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index bdcb1d45a..c89078cd3 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -283,6 +283,7 @@ static void extract_fsm(RTLIL::Wire *wire) fsm_cell->connections["\\CTRL_IN"] = ctrl_in; fsm_cell->connections["\\CTRL_OUT"] = ctrl_out; fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); + fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); module->cells[fsm_cell->name] = fsm_cell; |