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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-09 16:49:08 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-09 16:49:08 +0200 |
| commit | a429aedc0ff21b95ded89320144d2063234a3d7e (patch) | |
| tree | cbcf8861e769552875ab23fa36e4ebc2a4690e3e /passes | |
| parent | 7f8c420cf78eb41784fc6852524ba33074f84d64 (diff) | |
| parent | 810f8c5dbdcf3cdd043e4c0dd597c0a03cce3f8b (diff) | |
| download | yosys-a429aedc0ff21b95ded89320144d2063234a3d7e.tar.gz yosys-a429aedc0ff21b95ded89320144d2063234a3d7e.tar.bz2 yosys-a429aedc0ff21b95ded89320144d2063234a3d7e.zip | |
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
Cleanup synth_xilinx SRL inference, make more consistent
Diffstat (limited to 'passes')
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