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author | Clifford Wolf <clifford@clifford.at> | 2016-09-08 10:06:40 +0200 |
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committer | GitHub <noreply@github.com> | 2016-09-08 10:06:40 +0200 |
commit | 9e72046906bdb9a15054c6c54b0003bfdc3baf6e (patch) | |
tree | 3f12c8e961e70949ca16b93aa53bda6eec81ed36 /passes | |
parent | 209a3d9ffcb5f7efbe60b0e0d45755329532535e (diff) | |
parent | df4ab169a7ae84f9380e658e3ac5958a3d3e57d3 (diff) | |
download | yosys-9e72046906bdb9a15054c6c54b0003bfdc3baf6e.tar.gz yosys-9e72046906bdb9a15054c6c54b0003bfdc3baf6e.tar.bz2 yosys-9e72046906bdb9a15054c6c54b0003bfdc3baf6e.zip |
Merge pull request #225 from Kmanfi/test
Typo fix.
Diffstat (limited to 'passes')
-rw-r--r-- | passes/memory/memory_share.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index bcb7433a2..ca09ac52c 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -753,7 +753,7 @@ struct MemorySharePass : public Pass { log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); + log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n"); extra_args(args, 1, design); for (auto module : design->selected_modules()) MemoryShareWorker(design, module); |