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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 12:30:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 12:30:46 -0700 |
| commit | 96ee7b9cf7a6a9010bc820dc110bf945c35cb32e (patch) | |
| tree | b00d6708f2bf2e864bde89205e1d7f02a95195bb /passes | |
| parent | 7f10019610e9570549ddcb945da8ae048d718dfd (diff) | |
| download | yosys-96ee7b9cf7a6a9010bc820dc110bf945c35cb32e.tar.gz yosys-96ee7b9cf7a6a9010bc820dc110bf945c35cb32e.tar.bz2 yosys-96ee7b9cf7a6a9010bc820dc110bf945c35cb32e.zip | |
Simplify
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 11064e072..b387ca0a2 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -92,16 +92,12 @@ match ffFJKG endmatch code sigH sigO clock clock_pol - sigO = sigH; - if (ffFJKG) { sigH = port(ffFJKG, \Q); for (auto b : sigH) if (b.wire->get_bool_attribute(\keep)) reject; - sigO = sigH; - SigBit c = port(ffFJKG, \CLK).as_bit(); bool cp = param(ffFJKG, \CLK_POLARITY).as_bool(); @@ -111,6 +107,8 @@ code sigH sigO clock clock_pol clock = c; clock_pol = cp; } + + sigO = sigH; endcode match addA |