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| author | Clifford Wolf <clifford@clifford.at> | 2014-10-18 15:20:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-18 15:20:38 +0200 |
| commit | 84ffe04075bbddfd1b288295c07d036416923c3a (patch) | |
| tree | 1d3b80144cad20aeab554084d42e7ba592fc686e /passes | |
| parent | 85572b05e5359f28c1625b873dc14428f796a454 (diff) | |
| download | yosys-84ffe04075bbddfd1b288295c07d036416923c3a.tar.gz yosys-84ffe04075bbddfd1b288295c07d036416923c3a.tar.bz2 yosys-84ffe04075bbddfd1b288295c07d036416923c3a.zip | |
Fixed various VS warnings
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 | ||||
| -rw-r--r-- | passes/opt/share.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 8 |
3 files changed, 7 insertions, 7 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 4194f88c3..8a20898cf 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -112,7 +112,7 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo if (regs.check_any(s1) != regs.check_any(s2)) return regs.check_any(s2); if (direct_wires.count(w1) != direct_wires.count(w2)) - return direct_wires.count(w2); + return direct_wires.count(w2) != 0; if (conns.check_any(s1) != conns.check_any(s2)) return conns.check_any(s2); } diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 354586937..2496f15d3 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -747,7 +747,7 @@ struct ShareWorker forbidden_controls_cache[cell].insert(bits.begin(), bits.end()); } - log_assert(recursion_state.count(cell)); + log_assert(recursion_state.count(cell) != 0); recursion_state.erase(cell); return forbidden_controls_cache[cell]; @@ -862,7 +862,7 @@ struct ShareWorker activation_patterns_cache[cell].insert(c_patterns.begin(), c_patterns.end()); } - log_assert(recursion_state.count(cell)); + log_assert(recursion_state.count(cell) != 0); recursion_state.erase(cell); optimize_activation_patterns(activation_patterns_cache[cell]); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 510dcd60b..a02eafb96 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -108,7 +108,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool LibertyAst *best_cell = NULL; std::map<std::string, char> best_cell_ports; int best_cell_pins = 0; - float best_cell_area = 0; + double best_cell_area = 0; if (ast->id != "library") log_error("Format error in liberty file.\n"); @@ -144,7 +144,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool this_cell_ports[cell_rst_pin] = 'R'; this_cell_ports[cell_next_pin] = 'D'; - float area = 0; + double area = 0; LibertyAst *ar = cell->find("area"); if (ar != NULL && !ar->value.empty()) area = atof(ar->value.c_str()); @@ -204,7 +204,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo LibertyAst *best_cell = NULL; std::map<std::string, char> best_cell_ports; int best_cell_pins = 0; - float best_cell_area = 0; + double best_cell_area = 0; if (ast->id != "library") log_error("Format error in liberty file.\n"); @@ -236,7 +236,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo this_cell_ports[cell_clr_pin] = 'R'; this_cell_ports[cell_next_pin] = 'D'; - float area = 0; + double area = 0; LibertyAst *ar = cell->find("area"); if (ar != NULL && !ar->value.empty()) area = atof(ar->value.c_str()); |