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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-30 15:31:12 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-30 15:32:06 +0200 |
| commit | 817ae04ee0c445efaf83e9847d4956f2dae0d857 (patch) | |
| tree | 60d300cb70d62e69e6809fc8a4f0071e3e68f79a /passes | |
| parent | f7fdd99e45de5330b8f0cbb183c7b6e2ccc274b7 (diff) | |
| download | yosys-817ae04ee0c445efaf83e9847d4956f2dae0d857.tar.gz yosys-817ae04ee0c445efaf83e9847d4956f2dae0d857.tar.bz2 yosys-817ae04ee0c445efaf83e9847d4956f2dae0d857.zip | |
simcells: Fix reset polarity for $_DLATCH_???_ cells.
Diffstat (limited to 'passes')
0 files changed, 0 insertions, 0 deletions