aboutsummaryrefslogtreecommitdiffstats
path: root/passes
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2016-10-16 20:37:02 +0200
committerClifford Wolf <clifford@clifford.at>2016-10-16 20:37:02 +0200
commit74702b04c2775b062aa89b8a4704cd9135d2b048 (patch)
tree0b5f839506e44e3a31649cb5086663e69a218359 /passes
parentfa535c0b0041621d0128087cd0236cfd5eb36e48 (diff)
downloadyosys-74702b04c2775b062aa89b8a4704cd9135d2b048.tar.gz
yosys-74702b04c2775b062aa89b8a4704cd9135d2b048.tar.bz2
yosys-74702b04c2775b062aa89b8a4704cd9135d2b048.zip
Build fixes for VS 2015
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/attrmvcp.cc2
-rw-r--r--passes/techmap/techmap.cc3
2 files changed, 4 insertions, 1 deletions
diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc
index 50eaf61df..1537def00 100644
--- a/passes/techmap/attrmvcp.cc
+++ b/passes/techmap/attrmvcp.cc
@@ -93,6 +93,7 @@ struct AttrmvcpPass : public Pass {
for (auto cell : module->selected_cells())
for (auto &conn : cell->connections())
+ {
if (driven_mode) {
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
@@ -102,6 +103,7 @@ struct AttrmvcpPass : public Pass {
for (auto bit : sigmap(conn.second))
net2cells[bit].insert(cell);
}
+ }
for (auto wire : module->selected_wires())
{
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 96b88eb42..6784f48c3 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1170,8 +1170,9 @@ struct FlattenPass : public Pass {
worker.flatten_do_list.erase(mod->name);
}
} else {
- for (auto mod : vector<Module*>(design->modules()))
+ for (auto mod : vector<Module*>(design->modules())) {
while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
+ }
}
log("No more expansions possible.\n");