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author | whitequark <whitequark@whitequark.org> | 2020-06-03 16:00:40 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2020-06-04 00:02:12 +0000 |
commit | 66255dab4ef3f7257aec65bbbf5b1901f2ee1ebd (patch) | |
tree | 04291b943a8cf3807245ee9f6c369179c36a332b /passes | |
parent | 5d2b6d1394f504729c0f2670b87534ea7efaec4b (diff) | |
download | yosys-66255dab4ef3f7257aec65bbbf5b1901f2ee1ebd.tar.gz yosys-66255dab4ef3f7257aec65bbbf5b1901f2ee1ebd.tar.bz2 yosys-66255dab4ef3f7257aec65bbbf5b1901f2ee1ebd.zip |
flatten: simplify.
Flattening does not benefit from topologically sorting cells within
a module when processing them.
Diffstat (limited to 'passes')
-rw-r--r-- | passes/techmap/flatten.cc | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index f37be685b..82e697495 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -260,10 +260,6 @@ struct FlattenWorker SigMap sigmap(module); - TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells; - dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit; - dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell; - for (auto cell : module->selected_cells()) { if (!design->has(cell->type)) @@ -279,37 +275,6 @@ struct FlattenWorker continue; } - for (auto &conn : cell->connections()) - { - RTLIL::SigSpec sig = sigmap(conn.second); - sig.remove_const(); - - if (GetSize(sig) == 0) - continue; - - RTLIL::Module *tpl = design->module(cell->type); - RTLIL::Wire *port = tpl->wire(conn.first); - if (port && port->port_input) - cell_to_inbit[cell].insert(sig.begin(), sig.end()); - if (port && port->port_output) - for (auto &bit : sig) - outbit_to_cell[bit].insert(cell); - } - - cells.node(cell); - } - - for (auto &it_right : cell_to_inbit) - for (auto &it_sigbit : it_right.second) - for (auto &it_left : outbit_to_cell[it_sigbit]) - cells.edge(it_left, it_right.first); - - cells.sort(); - - for (auto cell : cells.sorted) - { - log_assert(cell == module->cell(cell->name)); - RTLIL::Module *tpl = design->module(cell->type); dict<IdString, RTLIL::Const> parameters(cell->parameters); |