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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:59:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:59:38 -0700 |
| commit | 5be4b00a0dad4c6fe281a0e925daeae26715f215 (patch) | |
| tree | 1a2491d7c1885ad384c22176c5b4e6617f9095c3 /passes | |
| parent | aa4a69f89be9fcdcf20ca1c28d67444b994ec479 (diff) | |
| download | yosys-5be4b00a0dad4c6fe281a0e925daeae26715f215.tar.gz yosys-5be4b00a0dad4c6fe281a0e925daeae26715f215.tar.bz2 yosys-5be4b00a0dad4c6fe281a0e925daeae26715f215.zip | |
opt_clean: improve warning message
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 72ecc30e7..f7de02164 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -473,7 +473,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose) goto next_wire; if (mapped_wire_bit != init[i]) { - log_warning("Initial value conflict for wire '%s' and value '%s'.\n", log_signal(wire_bit), log_signal(mapped_wire_bit)); + log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i])); goto next_wire; } } |